1. Field of the Invention
The invention relates to a semiconductor package, and more particularly, to a multi-chip semiconductor package.
2. Description of the Related Art
As electronic products are getting smaller and lighter, the packages for protecting and interconnecting IC chips also have the same trend.
With ever-increasing demands for miniaturization and higher operating speeds, multi-chip packages have become an attractive approach in a variety of electronic device. Multi-chip packages, which contain two or more chips in a single package, can help minimize the limitation in system operation speed. In addition, multi-chip packages are capable of decreasing the interconnection length between IC chips thereby reducing signal delays and access times.
Referring to FIG. 1, a conventional stacked chip package 10 includes a substrate 11 with a chip 12 disposed thereon. The chip 12 is electrically connected to the substrate 11 by a plurality of bumps 14. A chip 13 is stacked on the chip 12 and electrically connected to the chip 12 by a plurality of bumps 15. A sealant 16 is disposed on the substrate 11 and used to encapsulate the chips 12, 13 to protect these chips from damage.
However, the package 10 uses a substrate, not a leadframe to carry chips. Moreover, it is not feasible to stack another package on the package 10.
Referring to FIG. 2, U.S. Pat. No. 6,977,431 discloses a stackable semiconductor package 200. The package 200 includes a metal die pad 110, a plurality of metal leads 115, each of which includes an inner lead portion 120 embedded in a plastic sealant 170 and an outer lead portion 130 that is fully disposed outside of the sealant 170. The die pad 110 includes an approximately planar first surface 111 and an approximately planar second surface 112 that is opposed to the first surface 111. A chip 140 is positioned in the sealant 170 and mounted to the second surface 112 of the die pad 110. A plurality of conductive wires 160 electrically connects the chip 140 to the inner lead portions 120. The first surface 111 of the die pad 110 is fully exposed out of the first surface 171 of the sealant 170.
Referring to FIG. 3, the above-mentioned U.S. patent also discloses that another semiconductor package 300 is capable of being stacked on the first surface 171 of the sealant 170 of the package 200. The package 300 includes a die pad 210 with a chip 230 disposed on the upper surface thereof. A plurality of conductive wires 250 is used to electrically connect the chip 230 to the leads 220 surrounding die pad 210. The chip 230, upper surface of the die pad 210 and upper surfaces of the leads 220 are covered by a sealant 260. The lower surface of the die pad 210 and lower surfaces of the leads 220 are exposed out of the sealant 260. A conductive layer 270 made of such as metal solder or conductive epoxy-based material is disposed between the packages 200 and 300 so as to electrically connect the lower surface of the die pad 210 to the first surface 111 of the die pad 110 and to electrically connect the leads 220 to the inner lead portions 120 of the leads 115.
Although the assembly of the package 200 and package 300 contains two chips 140 and 230, the assembly uses two die pads 110, 210 to respectively carry the chips 140 and 230. This will cause an increase in material cost.
Accordingly, there exists a need to provide a multi-chip package to solve the above-mentioned problems.